1. Field of the Invention
The present invention relates to a clock monitor circuit and, more particularly to a clock monitor circuit and synchronous semiconductor memory device utilizing the clock monitor circuit for monitoring the presence of a clock signal irrespective of its period.
2. Description of the Prior Art
Generally, a clock monitor circuit is adapted to monitor whether an input clock signal is present in a device that is synchronously operated by the input clock signal. If an input clock signal is not detected, the device stops operating, thereby preventing unnecessary waste of electric power.
In this regard, U.S. Pat. No. 4,633,097 describes a clock monitor circuit that changes two charge storage nodes and allows output to maintain a logic high level when an input clocking signal is present and a logic low level when the clocking signal is not present. The circuit therein described comprises a CMOS transistor that monitors the presence of the clocking signal by charging a node. For this reason, one disadvantage in this clock monitor circuit is that circuit's output signal is delayed by its RC time constant. Moreover, the clock monitor circuit cannot be used in a system where the period of the clock signal is longer than the circuit's RC time constant.
In addition, U.S. Pat. No. 5,619,643 describes a clock monitor circuit that detects an error state in a clocking signal used in a microprocessor system. The clock monitor circuit determines whether a clocking signal is present or not by charging and discharging a capacitance. Accordingly, like the circuit described in U.S. Pat. No. 4,633,097, the circuit disclosed in U.S. Pat. No. 5,619,643 monitors the clock signal by applying an electric charge. Therefore, just like the circuit described in the '097 patent, the clock monitor circuit of the '643 patent has the disadvantage of not being able to be used in a system where the period of the clock signal is longer than the RC time constant of the circuit.
A conventional synchronous semiconductor memory device generally has two modes of operation. In an operation mode, operations arc synchronous with an externally input clock signal. In a standby mode, operations are stopped when the externally input clock signal is not present. However, because some circuits in the device operate irrespective of the clock signal, these circuits unnecessarily waste electric power during the standby mode.
To prevent this problem, conventional devices are provided with an additional power-down pin that stops all operations by applying a power-down signal when a user wants to utilize the standby mode in the device irrespective of the outside clock signal. However, providing an additional power down pin increases manufacturing costs.
Accordingly, a need remains for a clock monitor circuit that overcomes the problems associated with prior art clock monitor circuits.